In communication systems, the goal is to transport information from one physical location to another. It is preferred that the transport of this information is reliable, is fast and consumes a minimal amount of resources. In most cases, there are trade-offs that need to be dealt with. For example, error-free communications might be possible if there were no bandwidth, latency or power-consumption constraints on a communication channel and system, but in most applications there are some constraints that require some design for robustness. Each of these constraints can be measured and designed for.
For example, bandwidth is often measured in the number of bits representing the information being conveyed per unit time. Sometimes, information is conveyed in non-binary form, but that can typically be considered as binary data anyway. For example, if information is represented by a sequence of symbols selected from a symbol alphabet of four symbols, each symbol can represent conveyance of two bits. With symbol alphabets having a size that is not a power of two, fractional bits are involved or rounding is involved, as is well-known in the field of information theory. It is also known that some number of bits or symbols might have different information content and that bits or symbols with low information content, where the excess is often considered a redundancy that can be compressed out, used for error detection or correction, or for other uses. In some designs, bandwidth is measured by bits/second or symbols/second of non-redundant information conveyed or encoded information conveyed (possibly having some redundancy as required for error handling or other signaling).
Latency is often measured by the time delay between a sender having information (in the form of data, a message, signals, etc.) ready to send to a receiver over a channel and the time when the receiver can use that information. For example, for a channel between two chips, if there are eight wires and eight independent bits are conveyed at a time, the latency might be just the time of flight (signal speed times length of wire) plus the time needed to charge and discharge transistors or other circuit elements in the path. However, where some computation is needed to encode and decode the information, the time needed for that computation is added to the latency.
Power-consumption is often expressed as a function of the number of operations (logical, computing, etc.) that are needed per unit bits to communicate them. For example, a design where six logical operations are needed to convey eight bits of information, that might be considered twice as expensive, power-consumption wise, as a design where three logical operations are needed to convey eight bits of information. Often, what is important in a design is the average effort, as that more often reflects on the total power consumption, heat dissipation, etc. as compared with the minimum and maximum values. It is known that with a fast processor and proper coding, many operations per second can be performed with arbitrary complexity. For example, a conventional packet router often has a processor or a specialized chip that reads instructions from an instruction memory and performs the instructed operation. In such cases, the power-consumption measurement has to fairly include the power consumption of the processor, the instruction memory, etc., albeit amortized over the number of bits conveyed.
As is well-known, a processor and memory can perform arbitrarily complex operations (e.g., table lookups, Fast Fourier transformations, multiplications, arbitrary finite algebra, etc.) that cannot be performed by two or three logic gates, but some designs are so power-consumption and latency limited that the design only allows for a few logic gates. For example, if the communication channel is between two parts of a chip or between two chips, it might not be practical to insert a processor and instruction memory between those two parts, consuming chip or board real estate as well as power, in order to effect some particular communications scheme. As an example, network communications between two microwave relay stations might be made reliable by using transmission powers of multiple watts, multiple levels of convolutional coding, handshaking for acknowledgements and retransmission of lost packets, and the like, where the power needed to perform the computations is largely irrelevant relative to the power needed to send the signal over the medium, but none of that would be practical for communications between two chips on a circuit board or between two circuits on a chip where the power needed to perform any needed computational, circuit or logical operations would be much larger than what is needed to actual convey the signals.
Another consideration in a design is signal noise. To send more robust signals, the amplitude of the signals can be increased, but that might lead to increased noise in other parts of the channel or system, in addition to increased power consumption. Thus, all other things being equal, the system that uses lower amplitude signals might be preferred.
In many electronic devices, communication plays an important role regardless of the function these electronic devices fulfill. Most modern electronic devices contain integrated circuits (“IC”) that exchange information with one another. The information may also be exchanged between ICs connecting two different devices. In general, one refers to these two communication settings as chip-to-chip communication.
In chip-to-chip communication, the physical transfer of information takes place over a transmission medium that may use multiple transmission paths. Each of these transmission paths is able carry a signal measurable by some physical characteristic or quantity, such as an electric voltage signal, electric current signal, light intensity signal or other electromagnetic field strength measurable on a wire, fiber or other medium. Herein, for readability, such paths/media for transmission is referred to as a “wire” without intending to limit wires to specific examples and the physically measurable characteristic, quantity or phenomenon is referred to as a “signal” on that wire. While distinct wires may carry distinct signals, it is often the case that signals on one wire will induce undesirable signals on another wire, either by signal-to-signal noise, common mode noise or other known phenomenon.
Depending on the exact application, a wire may be a micro-strip on a printed circuit board (“PCB”), a metal wire integrated on an IC and connecting two components within the same chip and/or a bond wire connecting two chips that are mounted on top of each other in a package-on-package configuration. As used herein, “wire” can refer to any physical path between one IC to another that can carry a signal on that wire. This physical path may comprise several parts, such as a metal trace on a PCB, a bond wire, a coupling capacitor, a “through silicon via” (“TSV”) and a connector. It is to be understood that these parts may be included in the concept of a wire. Multiple wires may be used to communicate and multiple wires in parallel constitute a communications bus. Important parameters in chip-to-chip communications are the communication speed, the power consumption, the physical footprint of the communication bus and electronics, and the error performance. In most chip-to-chip communication systems, the error performance has to be very low (e.g., less than one error in 1012 bits) and a certain amount of energy is required to achieve the error performance.
The pin-efficiency, r, of a chip-to-chip communication system is defined as the number of bits transmitted per wire in each communication interval. The communication interval, T, is often small and may be in the order of, e.g., 10−10 seconds or less. Multiple wires may be used to achieve a required aggregate data rate. A high pin-efficiency is preferred over a low pin-efficiency since the former allows one to have a smaller physical footprint for the same total data rate. Furthermore, if one is able to increase the pin-efficiency, the frequency of communication may be lowered to achieve the target aggregate data rate which immediately leads to lower power consumption in most chip-to-chip communication systems.
There are several reasons why it is difficult to design high speed, low power, small footprint and low error-rate chip-to-chip communication systems. First, communication is not perfect and the signals transmitted on the wires are disturbed by noise and interference. In chip-to-chip communications some sources of noise are thermal noise, common-mode noise and interference, crosstalk, reference noise and switching noise. An important type of switching noise is simultaneous switching output (“SSO”) noise. SSO noise plays a large role at higher communication frequencies. The resilience against some of these noise types may be increased by increasing the transmit power. For others, such as SSO noise and crosstalk, increasing the transmit power is not beneficial since these noise types tend to increase as well.
A second impairment of chip-to-chip communications is that the physical medium tends to attenuate the signals transmitted on the wires. Especially when the data rate increases and/or the wires become longer, attenuation will increase. This requires one to increase transmission power burned in the drivers and use equalization methods. Since a large part of the power consumption consists of the power burned in the drivers the total power consumption has to increase to combat the attenuation.
To combat the issues with respect to common-mode noise, crosstalk, and SSO noise many chip-to-chip communication systems use differential signaling. In differential signaling an information carrying signal is encoded into the difference of two signals. Each of these encoded signals is transmitted on a separate wire. Differential signaling provides immunity against common-mode noise and interference and one can use a transmitter architecture that minimizes SSO noise. A major downside of differential signaling is that the pin-efficiency is only r=0.5. To achieve high data rates one would have to run at very high frequencies where attenuation is high. One would like to use signaling methods for chip-to-chip communications that preserve the excellent properties of differential signaling but operate at a significantly higher pin-efficiency. Furthermore, these methods should allow for an efficient implementation in terms of circuitry and lead to a power-efficient operation.
Some systems have been devised to deal with the constraints explained above, including some previously developed by the inventors named in the present application.
FIG. 1 illustrates generally a conventional chip-to-chip communication system that uses differential signaling. The system is shown comprising a transmit unit 100 connected by a communication bus 120 to a receive unit 150. Transmit unit 100 comprises a driver unit 110 that drives two wires 122 of bus 120. Driver unit 110 generates two signals 112 and 114, denoted in the figure by s0 and s1, based on the information to be transmitted on bus 120. Driver 110 may drive the wires of bus 120 in voltage-mode or current-mode. Bus 120 may be terminated at the receiver by a termination resistor 130 and at the transmitter by a termination resistor 132. A differential amplifier or comparator 140 measures the voltage across termination resistor 130 and detects the data transmitted on bus 120.
For differential signaling, these two signals satisfy s0=−s1 and this property gives differential signaling its excellent properties with respect to common-mode noise and crosstalk. Driver 110 may perform additional tasks, such as amplification, pre-emphasis and equalization. Differential amplifier 140 may perform additional tasks, such as de-emphasis, equalization and equalization. By “perform tasks”, it should be understood that performance can be implemented using particular circuitry and/or physically-implemented logical elements.
FIG. 1 also shows that transmit unit 100 is connected to a positive terminal 160 of a power supply (not shown) and a ground terminal 162. Terminals 150 and 162 supply transmit unit 100 with a voltage of Vdd volts. The circuitry of transmit unit 100 requires a power supply to operate. A parasitic inductor 164 impairs the connection to Vdd, while a parasitic inductor 166 impairs the connection to ground terminal 162. Parasitic inductors 164, 166 might be a result of, e.g., a bondwire and/or impedance discontinuity in an IC package, as is known. When circuitry in transmit unit 100 causes variations in currents through parasitic inductors 164, 166, a voltage develops across those parasitic inductors, which causes a drop in power supply voltage for circuitry in transmit unit 100 and this may cause the signals transmitted on bus 120 to be disturbed. The time-varying current through parasitic inductors 164, 166 is largely determined by the signaling method. For binary differential signaling, the variation is minimal, since s0=−s1.
FIG. 2 illustrates the use differential signaling with multiple wires, on a chip-to-chip communication system. FIG. 2 shows a chip-to-chip communication system where communication takes place over a bus 220 comprising 2n wires 235 between a transmit unit 200 and a receive unit 250. Transmit unit 200 comprises n drivers 260 that each implement differential signaling of an input signal (not shown). Each of these drivers 260 is connected to a different pair of wires of communication bus 220. The wires 235 of communication bus 220 can be terminated at transmit unit 200 and/or receive unit 250. At receive unit 250, differential receivers or comparators 270 sense the signals on each pair of wires. Drivers 260 in transmit unit 200 are connected to a positive power supply 280 and a ground 282. Both connections are through parasitic inductors 284 and 286, respectively. Since differential transmitters are used, the variation of the currents through parasitic inductors 284 and 286 may be small. The reason for this is clear when binary differential signaling is used and the bus is driven in current-mode. In that instance, each of drivers 260 sources a current of some strength I into one of the wires of the wire pair and sinks a current of that strength I from the other wire of the wire pair. The sum of all currents that is sourced by drivers 260 is supplied though parasitic inductor 284 and is constant. The sum of all currents that is sunk by drivers 260 is sunk into ground 282 through parasitic inductor 286 and is constant as well. Hence the introduction of SSO is minimized. One may require multiple connections to Vdd and ground to limit the current through each of these connections. SSO is also minimized, as should be apparent.
A major drawback of using binary differential signaling is that the pin-efficiency, r, is only r=0.5. To achieve a bitrate of fb bits per wire, the symbol rate or frequency of operation per wire has to be 2fb. For high-speed operation and/or for longer transmission paths, the amount of power spent in the drivers has to increase substantially to mitigate the effects of attenuation. To achieve a higher pin-efficiency with differential signaling, one can opt for multi-level differential signaling. Although this leads to higher pin-efficiencies, the required transmission power to assure reliable communication may increase faster than the advantages obtained from a potentially lower symbol rate.
In [Poulton], a multi-wire differential signaling scheme was proposed that indicated a potential to obtain higher pin-efficiencies than differential signaling. The scheme disclosed in [Poulton] retains several of the noise resilience properties of differential signaling, but creates other problems.
[Poulton] only teaches how to implement pin-efficient schemes for three and four wires, but often transmission takes place over a bus of more than four wires. Also, as pointed out in [Poulton], the method disclosed there is not very power-efficient. A signaling method that achieves high pin-efficiency and is power efficient is therefore preferred. Finally, encoding and decoding the signaling method as disclosed in [Poulton] is not straightforward, especially when the number of wires is more than four and therefore much power might be consumed in just the processing and handling of signaling.
[Horowitz] describes a signaling method that reduces SSO. The method in [Horowitz] is based on multi-level signaling where the sum of the signal levels transmitted on the bus is kept close to each other from bus cycle to bus cycle. There are several problems to this approach. First, for the method to have maximum effect, all driver circuitry has to use a single connection to Vdd and a single connection to ground. This is only possible for a small number of bus wires such that the total required current can be limited. Second, encoding and decoding such signaling schemes is only possible for a small number of bus wires to avoid overly complex encoding and decoding. Third, introducing memory between consecutive bus cycles increases the delay of the bus communication system.
In Cronie I, orthogonal differential vector signaling (“ODVS”) is described. ODVS allows for chip-to-chip communications with a pin-efficiency larger than that of differential signaling (up to r=1.0) with a resilience against several types of noise similar to that of differential signaling. Where even larger pin-efficiencies are needed, the teachings of Cronie II and Cronie III can be applied.
Cronie II and Cronie III teach that spherical codes can be used to obtain pin-efficiencies larger than r=1.0. In some embodiments, these spherical codes are permutation modulation codes (as in Cronie II) or sparse signaling codes (as in Cronie III). These codes lead to pin-efficient and noise resilient chip-to-chip communications, while keeping the power consumption of transmitter and receiver low compared to conventional signaling methods. In certain cases, encoding the signaling schemes of Cronie III for pin-efficiencies larger than r=1.0 can be simplified. Furthermore, for high pin-efficiencies and some of the signaling schemes of Cronie III, hardware architectures that effectively mitigate SSO noise can also be simplified.
Yet some application might still require more power-efficient signaling methods that provide a pin-efficiency larger than r=0.5 and provide SSO resilience with an efficient hardware architecture, with a good performance with respect to common-mode noise and interference.